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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 lp3869x-adj/q1 500-ma low-dropout cmos linear regulators stable with ceramic output capacitors 1 1 features 1 ? wide input voltage range: 2.7 v to 10 v ? all wson options are available as aec-q100 grade 1 ? output voltage range: 1.25 v to 9 v ? 2% adjust (adj) pin voltage accuracy (25 c) ? low dropout voltage: 250 mv at 500 ma (typical, 5-v out) ? precision (trimmed) bandgap reference ? ensured specs for ? 40 c to +125 c ? 1- a off-state quiescent current ? thermal overload protection ? foldback current limiting ? ground (gnd) pin current: 55 a (typical) at full load ? enable (en) pin (lp38693-adj) 2 applications ? hard disk drives ? notebook computers ? battery-powered devices ? portable instrumentation 3 description the lp3869x-adj low-dropout cmos linear regulators provide 2% precision reference voltage, extremely low dropout voltage (250 mv at 500-ma load current, v out = 5 v), and excellent ac performance using ultra-low equivalent series resistance (esr) ceramic output capacitors. the low thermal resistance of the wson and sot- 223 packages allow use of the full operating current even in high ambient temperature environments. the use of a pmos power transistor means that no dc base drive current is required to bias it, thus allowing the gnd-pin current to remain below 100 a regardless of load current, input voltage, or operating temperature. device information (1) part number package body size (nom) lp38691-adj wson (6) 3.00 mm 3.00 mm lp38693-adj sot-223 (5) 6.50 mm 3.56 mm wson (6) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application circuits v out = v adj (1 + r1/r2) * minimum value required for stability lp38693 -adj in out gnd 1 p f * 1 p f * v out v in r1 r2 v en en adj lp38691 -adj in out gnd 1 p f * 1 p f * v out v in r1 r2 adj productfolder sample &buy technical documents tools & software referencedesign support &community
2 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings: lp38691-adj, lp38693-adj ............. 4 6.3 esd ratings: lp38691-adj-q1, lp38693-adj-q1 . 4 6.4 recommended operating conditions ....................... 4 6.5 thermal information .................................................. 4 6.6 electrical characteristics ........................................... 5 6.7 typical characteristics .............................................. 6 7 detailed description ............................................ 11 7.1 overview ................................................................. 11 7.2 functional block diagrams ..................................... 11 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 12 8 application and implementation ........................ 13 8.1 application information ............................................ 13 8.2 typical applications ............................................... 13 9 power supply recommendations ...................... 18 10 layout ................................................................... 18 10.1 layout guidelines ................................................. 18 10.2 layout examples ................................................... 18 10.3 wson mounting ................................................... 19 11 device and documentation support ................. 20 11.1 documentation support ........................................ 20 11.2 related links ........................................................ 20 11.3 community resources .......................................... 20 11.4 trademarks ........................................................... 20 11.5 electrostatic discharge caution ............................ 20 11.6 glossary ................................................................ 20 12 mechanical, packaging, and orderable information ........................................................... 20 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision j (october 2015) to revision k page ? added caution note to foldback current limiting subsection ............................................................................................ 12 changes from revision i (april 2013) to revision j page ? added device information and pin configuration and functions sections, esd ratings table, update thermal values; add feature description , device functional modes , application and implementation , power supply recommendations , layout , device and documentation support , and mechanical, packaging, and orderable information sections; update vin, vout and ven pin names to in, out, and en in text and graphics; modified wording of description to eliminate redundancy; added top nav icon for reference design. .................................................. 1 changes from revision h (april 2013) to revision i page ? changed layout of national data sheet to ti format ........................................................................................................... 15 ? changed layout of national data sheet to ti format .......................................................................................................... 19
3 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 5 pin configuration and functions ngg package 6-pin wson with exposed thermal pad lp38691-adj top view ngg package 6-pin wson with exposed thermal pad lp38693-adj top view nc - no internal connection ndc package 5-pin sot-223 lp38693-adj top view pin functions pin i/o description lp38691-adj lp38693-adj name wson wson sot-223 dap ? ? wson only - the dap (exposed pad) functions as a thermal connection when soldered to a copper plane. see wson mounting section for more information. en ? 3 1 i the en pin allows the part to be turned to an on or off state by pulling this pin high or low. gnd 2 2 5 ? circuit ground for the regulator. for the sot-223 package this is thermally connected to the die and functions as a heat sink when the soldered down to a large copper plane. in 1, 6 1, 6 4 i this is the input supply voltage to the regulator. for wson devices, both in pins must be tied together for full current operation (250 ma maximum per pin). n/c 3 ? ? ? no internal connection. adj 4 4 2 o the adj pin is used to set the regulated output voltage by connecting it to the external resistors r1 and r2 (see typical application circuits ). out 5 5 3 i regulated output voltage. in 2 3 4 5 6 1 gnd en adj out in exposed pad on bottom (dap) adj out gnd en in 12 4 3 5 in 2 3 4 5 6 1 gnd n/c adj out in exposed pad on bottom (dap)
4 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) if military/aerospace specified devices are required, contact the texas instruments sales office/ distributors for availability and specifications. (3) if used in a dual-supply system where the regulator load is returned to a negative supply, the out pin must be diode clamped to ground. (4) at elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). when using the wson package, refer to leadless leadframe package (llp) ( snoa401 ) and the wson mounting section in this data sheet. if power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit v (max) all pins (with respect to gnd) ? 0.3 12 v i out (3) internally limited v power dissipation (4) internally limited v junction temperature ? 40 150 c storage temperature, t stg ? 65 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. 6.2 esd ratings: lp38691-adj, lp38693-adj value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.3 esd ratings: lp38691-adj-q1, lp38693-adj-q1 value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v 6.4 recommended operating conditions min nom max unit v in supply voltage 2.7 10 v operating junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . (2) thermal resistance value r ja is based on the eia/jedec high-k printed circuit board defined by: jesd51-7 - high effective thermal conductivity test board for leaded surface mount packages. (3) the pcb for the wson (ngn) package r ja includes thermal vias under the exposed thermal pad per eia/jedec jesd51-5. 6.5 thermal information thermal metric (1) lp3869x-adj lp38693-adj unit wson sot-223 6 pins 5 pins r ja (2) junction-to-ambient thermal resistance, high-k 50.6 68.5 (3) c/w r jc(top) junction-to-case (top) thermal resistance 44.4 52.2 r jb junction-to-board thermal resistance 24.9 13.0 jt junction-to-top characterization parameter 0.4 5.5 jb junction-to-board characterization parameter 25.1 12.8 r jc(bot) junction-to-case (bottom) thermal resistance 5.4 n/a
5 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated (1) typical numbers represent the most likely parametric norm for 25 c operation. (2) output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. (3) output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1 ma to full load. (4) dropout voltage is defined as the minimum input to output differential required to maintain the output within 100 mv of nominal value. 6.6 electrical characteristics unless otherwise specified, limits apply for t j = 25 c, v in = v out + 1 v, c in = c out = 10 f, i load = 10 ma. minimum and maximum limits are specified through testing, statistical correlation, or design. parameter test conditions min typ (1) max unit v adj adj pin voltage v in = 2.7 v 1.225 1.25 1.275 v 3.2 v v in 10 v, 100 a < i l < 0.5 a 1.25 3.2 v v in 10 v, 100 a < i l < 0.5 a full operating temperature range 1.2 1.3 v out / v in output voltage line regulation (2) v out + 0.5 v v in 10 v i l = 25 ma 0.03 %/v v out + 0.5 v v in 10 v i l = 25 ma full operating temperature range 0.1 v out / i l output voltage load regulation (3) 1 ma < i l < 0.5 a v in = v out + 1 v 1.8 %/a 1 ma < i l < 0.5 a v in = v out + 1 v full operating temperature range 5 v do dropout voltage (4) (v out = 2.5 v) i l = 0.1 a 80 mv i l = 0.5 a 430 (v out = 2.5 v) full operating temperature range i l = 0.1 a 145 i l = 0.5 a 725 (v out = 3.3 v) i l = 0.1 a 65 i l = 0.5 a 330 (v out = 3.3 v) full operating temperature range i l = 0.1 a 110 i l = 0.5 a 550 (v out = 5 v) i l = 0.1 a 45 i l = 0.5 a 250 (v out = 5 v) full operating temperature range i l = 0.1 a 100 i l = 0.5 a 450 i q quiescent current v in 10 v, i l =100 a ? 0.5 a 55 a v in 10 v, i l =100 a ? 0.5 a full operating temperature range 100 v en 0.4 v, (lp38693 only) 0.001 1 i l(min) minimum load current v in ? v out 4 v full operating temperature range 100 i fb foldback current limit v in ? v out > 5 v 350 ma v in ? v out < 4 v 850 psrr ripple rejection v in = v out + 2 v(dc), with 1 v(p-p) / 120-hz ripple 55 db t sd thermal shutdown activation (junction temp) 160 c t sd (hyst) thermal shutdown hysteresis (junction temp) 10 i adj adj input leakage current v adj = 0 v to 1.5 v, v in = 10 v ? 100 0.01 100 na e n output noise bw = 10 hz to 10 khz v out = 3.3 v 0.7 v/ hz v out (leak) output leakage current v out = v out(nom) + 1 v at 10 v in 0.5 2 a
6 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated electrical characteristics (continued) unless otherwise specified, limits apply for t j = 25 c, v in = v out + 1 v, c in = c out = 10 f, i load = 10 ma. minimum and maximum limits are specified through testing, statistical correlation, or design. parameter test conditions min typ (1) max unit v en enable voltage (lp38693 only) output = off state full operating temperature range 0.4 v output = on state, v in = 4 v full operating temperature range 1.8 output = on state, v in = 6 v full operating temperature range 3 output = on state, v in = 10 v full operating temperature range 4 i en en pin leakage (lp38693 only) v en = 0 v or 10 v, v in = 10 v ? 1 0.001 1 a 6.7 typical characteristics unless otherwise specified: t j = 25 c, c in = c out = 10 f, en pin is tied to in (lp38693-adj only), v out = 1.25 v, v in = v out 1 v, i load = 10 ma. figure 1. noise vs frequency figure 2. noise vs frequency figure 3. noise vs frequency figure 4. ripple rejection 10 100 1k 10k 100k frequency (hz) 0.0 0.5 1.0 1.5 noise ( p v/ hz) c out = 100 p f 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 frequency (hz) ripple rejection (db) v in (dc) = 3.25v v in (ac) = 1v(p-p) c out = 10 p f frequency (hz) 10 100 1k 10k 100k 0.0 0.2 0.4 0.6 0.8 1.0 noise ( p v/ hz) c out = 10 p f 10 100 1k 10k 100k frequency (hz) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 noise/ ( p v hz) c out = 1 p f
7 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, en pin is tied to in (lp38693-adj only), v out = 1.25 v, v in = v out 1 v, i load = 10 ma. figure 5. ripple rejection figure 6. ripple rejection figure 7. v ref vs temperature figure 8. line transient response figure 9. line transient response figure 10. line transient response 20 10 0 -10 -20 ' v out (mv) 3 4 5 v in (v) v in v out v out = 3.3v c out = 100 p f 200 p s/div 40 20 0 -20 -40 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v c out = 10 p f 200 p s/div -50 -25 0 25 50 75 100 125 temperature ( o c) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 % deviation 20 10 0 -10 -20 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v c out = 100 p f 200 p s/div 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 frequency (hz) ripple rejection (db) v in (dc) = 3.25v v in (ac) = 1v(p-p) c out = 1 p f 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 frequency (hz) ripple rejection (db) v in (dc) = 3.25v v in (ac) = 1v(p-p) c out = 100 p f
8 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, en pin is tied to in (lp38693-adj only), v out = 1.25 v, v in = v out 1 v, i load = 10 ma. figure 11. line transient response figure 12. line transient response figure 13. line transient response figure 14. load transient response figure 15. load transient response figure 16. en voltage vs temperature v en (v) v in = 10v v in = 6v v in = 4v 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 -50 -25 0 25 50 75 100 125 temperature ( o c) 400 200 0 -200 -400 ' v out (mv) 0.01 0.5 i load (a) i load v out c out = 1 p f 10 p s/div 200 100 0 -100 -200 ' v out (mv) 0.01 0.5 i load (a) i load v out c out = 10 p f 40 p s/div 100 50 0 -50 -100 ' v out (mv) 3 4 5 v in (v) v in v out v out = 3.3v 100 p s/div c out = 1 p f 100 50 0 -50 -100 ' v out (mv) 3 4 5 v in (v) v in v out v out = 3.3v c out = 10 p f 100 p s/div 100 50 0 -50 -100 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v 40 p s/div c out = 1 p f
9 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, en pin is tied to in (lp38693-adj only), v out = 1.25 v, v in = v out 1 v, i load = 10 ma. figure 17. load regulation vs temperature figure 18. line regulation vs temperature v out = 1.25 v figure 19. v out vs v in v out = 1.8 v figure 20. v out vs v in figure 21. v out vs. v in , power-up figure 22. v out vs. v en , on (lp38693-adj only) ' v out / ' i out (%/a) -50 -25 0 25 50 75 100 125 temperature ( o c) -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -50 -25 0 25 50 75 100 125 temperature ( o c) 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 ' v out / ' v in (%/v)
10 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, en pin is tied to in (lp38693-adj only), v out = 1.25 v, v in = v out 1 v, i load = 10 ma. figure 23. v out vs. v en , off (lp38693-adj only) figure 24. min v out vs. i out v out = 1.8 v figure 25. dropout voltage vs. i out 0 100 200 300 400 500 i out (ma) 0 100 200 300 400 500 600 700 800 900 v dropout (mv) -40c 25c 125c 0 100 200 300 400 500 2 2.1 2.2 2.3 2.4 2.5 2.6 min v in (v) i out (ma) -40c 25c 125c
11 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the lp3869x-adj devices are designed to meet the requirements of portable, battery-powered digital systems providing an accurate output voltage with fast start-up. when disabled via a low logic signal at the enable pin (en), the power consumption is reduced to virtually zero (lp38693-adj only). these lp3869x-adj devices perform well with a single 1- f input capacitor and a single 1- f ceramic output capacitor. 7.2 functional block diagrams figure 26. lp38691 functional diagram (wson) figure 27. lp38693 functional diagram (sot-223, wson) enable logic - + mosfet driver foldback current limiting 1.25-v reference thermal shutdown in out gnd p-fet p-fet n/c adj enable logic - + mosfet driver foldback current limiting 1.25-v reference thermal shutdown in out gnd p-fet p-fet en adj
12 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 7.3 feature description 7.3.1 enable (en) the lp38693-adj has an enable pin (en) which allows an external control signal to turn the regulator output to either an on or off state. the enable on/off threshold has no hysteresis. the voltage signal must rise and fall cleanly, and promptly, through the on and off voltage thresholds. the en pin voltage must be higher than the v en(min) threshold to ensure that the device is fully enabled under all operating conditions. the en pin voltage must be lower than the v en(max) threshold to ensure that the device is fully disabled. the en pin has no internal pullup or pulldown to establish a default condition and, as a result, this pin must be terminated either actively or passively. if the en pin is driven from a source that actively pulls high and low, the drive voltage should not be allowed to go below ground potential or higher than v in . if the application does not require the enable function, the en pin should be connected directly to the in pin. 7.3.2 thermal overload protection (t sd ) thermal shutdown disables the output when the junction temperature rises to approximately 160 c which allows the device to cool. when the junction temperature cools to approximately 150 c, the output circuitry enables. based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. this thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating. the t sd circuitry of the lp38693 has been designed to protect against temporary thermal overload conditions. the t sd circuitry was not intended to replace proper heat-sinking. continuously running the lp38693 device into thermal shutdown degrades device reliability. 7.3.3 foldback current limiting foldback current limiting is built into the lp3869x-adj devices which reduces the amount of output current the part can deliver as the output voltage is reduced. the amount of load current is dependent on the differential voltage between the v in and v out . typically, when this differential voltage exceeds 5 v, the load current will limit at about 350 ma. when the v in ? v out differential is reduced below 4 v, load current is limited to about 850 ma. caution when toggling the lp38693 enable (en) after the input voltage (v in ) is applied, the foldback current limit circuitry is functional the first time that the en pin is taken high. the foldback current limit circuitry is non-functional the second, and subsequent, times that the en pin is taken high. depending on the input and output capacitance values the input inrush current may be higher than expected which can cause the input voltage to droop. if the en pin is connected to the in pin, the foldback current limit circuitry is functional when v in is applied if v in starts from less than 0.4 v. 7.4 device functional modes 7.4.1 enable (en) the lp38693-adj may be switched to the on or off state by logic input at the en pin. a logic-high voltage on the en pin turns the device to the on state. a logic-low voltage on the en pin turns the device to the off state. if the application does not require the shutdown feature, the en pin must be tied to v in to keep the regulator output permanently in the on state when power is applied. to ensure proper operation, the signal source used to drive the en input must be able to swing above and below the specified turnon or turnoff voltage thresholds listed in the electrical characteristics section under v en .
13 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lp3869x-adj can provide 500 ma output current with 2.7 v to 10 v input. adjustable output voltage in the range of 1.25 v to 9 v. lp3869x-adj is stable with a 1- f ceramic output capacitor. typical output noise is 0.7 v rms at frequencies from 10 hz to 10 khz. typical pssr is 55 db at 1 khz. 8.2 typical applications * minimum value required for stability figure 28. lp38691-adj typical application * minimum value required for stability figure 29. lp38693-adj typical application 8.2.1 design requirements for typical ldo cmos linear regulators , use the parameters listed in table 1 . table 1. design parameters design parameters example value input voltage range 2.7 v to 10 v output range adjustable output current 500 ma (maximum) output capacitor range 1 f lp38693 -adj in out gnd 1 p f * 1 p f * v out v in r1 r2 v en en adj lp38691 -adj in out gnd 1 p f * 1 p f * v out v in r1 r2 adj
14 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 8.2.2 detailed design procedure 8.2.2.1 setting the output voltage the output voltage is set using the external resistors r1 and r2 (see typical applications . the output voltage will be given by equation 1 : v out = v adj (1 + ( r1 / r2 )) (1) because the part has a minimum load current requirement of 100 a, it is recommended that r2 always be 12 k or less to provide adequate loading. even if a minimum load is always provided by other means, it is not recommended that very high value resistors be used for r1 and r2 because it can make the adj node susceptible to noise pickup. a maximum ohmic value of 100 k is recommended for r2 to prevent this from occurring. 8.2.2.2 external capacitors in common with most regulators, the lp3869x-adj devices require an external capacitors for regulator stability. the devices are specifically designed for portable applications requiring minimum board space and smallest components. these capacitors must be correctly selected for good performance. 8.2.2.3 input capacitor an input capacitor of at least 1 f is required (ceramic recommended). the capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground. 8.2.2.4 output capacitor an output capacitor is required for loop stability. it must be located less than 1 centimeter from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them. the minimum amount of output capacitance that can be used for stable operation is 1 f. ceramic capacitors are recommended; the lp3869x-adj devices were designed for use with ultra-low equivalent series resistance (esr) capacitors. the lp3869x-adj is stable with any output capacitor esr between 5 m to 500 m . 8.2.2.5 capacitor characteristics it is important that capacitance tolerance and variation with temperature be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. 8.2.2.5.1 ceramic capacitors for values of capacitance in the 10- to 100- f range, ceramics are usually larger and more costly than tantalums but give superior ac performance for bypassing high frequency noise because of very low esr (typically less than 10 m ). however, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. the lp3869x-adj is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. for capacitance values in the range of 0.47 f to 4.7 f, ceramic capacitors are the smallest, least expensive and have the lowest esr values, thus making them best for eliminating high frequency noise. the esr of a typical 1- f ceramic capacitor is in the range of 20 m ? to 40 m ? , which easily meets the esr requirement for stability for the lp3869x. z5u and y5v dielectric ceramics have capacitance that drops severely with applied voltage. a typical z5u or y5v capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. the z5u and y5v also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. x7r and x5r dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within 20% of nominal over full operating ratings of temperature and voltage. of course, they are typically larger and more costly than z5u/y5u types for a given voltage and capacitance.
15 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 8.2.2.5.2 tantalum capacitors solid tantalum capacitors have good temperature stability: a high-quality tantalum capacitor typically shows a capacitance value that varies less than 10-15% across the full temperature range of -40 c to 125 c. esr will vary only about 2 going from the high to low temperature limits. the increasing esr at lower temperatures can cause oscillations when marginal quality capacitors are used (if the esr of the capacitor is near the upper limit of the stability range at room temperature). 8.2.2.6 rfi/emi susceptibility radio frequency interference (rfi) and electromagnetic interference (emi) can degrade the performance of any integrated circuit because of the small dimensions of the geometries inside the device. in applications where circuit sources are present which generate signals with significant high frequency energy content ( > 1 mhz), care must be taken to ensure that this does not affect the device regulator. if rfi/emi noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the device. if a load is connected to the device output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the device output. because the bandwidth of the regulator loop is less than 100 khz, the control circuitry cannot respond to load changes above that frequency. this means the effective output impedance of the device at frequencies above 100 khz is determined only by the output capacitors. in applications where the load is switching at high speed, the output of the device may need rf isolation from the load. it is recommended that some inductance be placed between the output capacitor and the load, and good rf bypass capacitors be placed directly across the load. pcb layout is also critical in high noise environments, because rfi/emi is easily radiated directly into pc traces. noisy circuitry should be isolated from clean circuits where possible, and grounded through a separate path. at mhz frequencies, ground planes begin to look inductive and rfi/ emi can cause ground bounce across the ground plane. in multi-layer pcb applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. 8.2.2.7 output noise noise is specified in two ways: ? spot noise or output noise density is the rms sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1-hz bandwidth). this type of noise is usually plotted on a curve as a function of frequency. ? total output noise or broad-band noise is the rms sum of spot noise over a specified bandwidth, usually several decades of frequencies. attention should be paid to the units of measurement. spot noise is measured in units v hz or nv hz, and total output noise is measured in v rms . the primary source of noise in low-dropout regulators is the internal reference. noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. increasing the area will decrease the chance of fitting the die into a smaller package. increasing the current drawn by the internal reference increases the total supply current (gnd pin current). 8.2.2.8 power dissipation knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with equation 2 . p d(max) = (v in(max) ? v out ) i out(max) (2) power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (v do ). however, keep in mind that higher voltage drops result in better dynamic (that is, psrr and transient) performance.
16 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated on the wson (drv) package, the primary conduction path for heat is through the exposed power pad to the pcb. to ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal ground plane with an appropriate amount of copper pcb area . on the vssop (dgk) and sot-223 (ndc) packages, the primary conduction path for heat is through the pins to the pcb. the maximum allowable junction temperature (t j(max) ) determines maximum power dissipation allowed (p d(max) ) for the device package. power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (r ja ) of the combined pcb and device package and the temperature of the ambient air (t a ), according to equation 3 or equation 4 : t j(max) = t a(max) + (r ja p d(max) ) (3) p d(max) = (t j(max) - t a(max) ) / r ja (4) unfortunately, this r ja is highly dependent on the heat-spreading capability of the particular pcb design, and therefore varies according to the total copper area, copper weight, and location of the planes. the r ja recorded in thermal information is determined by the specific eia/jedec jesd51-7 standard for pcb and copper- spreading area, and is to be used only as a relative measure of package thermal performance. for a well- designed thermal layout, r ja is actually the sum of the package junction-to-case (bottom) thermal resistance (r jcbot ) plus the thermal resistance contribution by the pcb copper area acting as a heat sink. 8.2.2.9 estimating junction temperature the eia/jedec standard recommends the use of psi ( ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical pcb board application. these characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. these psi metrics are determined to be significantly independent of copper-spreading area. the key thermal characteristics ( jt and jb ) are given in thermal information and are used in accordance with equation 5 or equation 6 . t j(max) = t top + ( jt p d(max) ) where ? p d(max) is explained in equation 2 . ? t top is the temperature measured at the center-top of the device package. (5) t j(max) = t board + ( jb p d(max) ) where ? p d(max) is explained in equation 2 . ? t board is the pcb surface temperature measured 1-mm from the device package and centered on the package edge. (6) for more information about the thermal characteristics jt and jb , see the ti application report semiconductor and ic package thermal metrics ( spra953 ), available for download at www.ti.com . for more information about measuring t top and t board , see the ti application report using new thermal metrics ( sbva025 ), available for download at www.ti.com . for more information about the eia/jedec jesd51 pcb used for validating r ja , see the ti application report thermal characteristics of linear and logic packages using jedec pcb designs ( szza017 ), available for download at www.ti.com .
17 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 8.2.2.10 reverse voltage a reverse voltage condition will exist when the voltage at the out pin is higher than the voltage at the in pin. typically this will happen when v in is abruptly taken low and c out continues to hold a sufficient charge such that the input to output voltage becomes reversed. a less common condition is when an alternate voltage source is connected to the output. there are two possible paths for current to flow from the out pin back to in during a reverse voltage condition. 1. while v in is high enough to keep the control circuity alive, and the en pin (lp38693-adj only) is above the v en(on) threshold, the control circuitry will attempt to regulate the output voltage. if the input voltage is less than the programmed output voltage, the control circuit will drive the gate of the pass element to the full on condition. in this condition, reverse current will flow from the out to the in pin, limited only by the r ds(on) of the pass element and the output to input voltage differential. discharging an output capacitor up to 1000 f in this manner will not damage the device as the current will rapidly decay. however, continuous reverse current should be avoided. when the en pin is low, this condition will be prevented. 2. the internal pfet pass element has an inherent parasitic diode. during normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. however, when v in is below the value where the control circuity is alive, or the en pin is low (lp38693-adj only), and the output voltage is more than 500 mv (typical) above the input voltage the parasitic diode becomes forward biased and current flows from the output pin to the input pin through the diode. the current in the parasitic diode should be limited to less than 1-a continuous and 5-a peak. if used in a dual-supply system where the regulator output load is returned to a negative supply, the out pin must be diode clamped to ground to limit the negative voltage transition. a schottky diode is recommended for this protective clamp. 8.2.3 application curve figure 30. line transient response 40 20 0 -20 -40 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v c out = 10 p f 200 p s/div
18 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 9 power supply recommendations the lp3869x-adj devices are designed to operate from an input supply voltage range of 2.7 v to 10 v. the input supply should be well regulated and free of spurious noise. to ensure that the device output voltage is well regulated, input supply should be at least v out + 0.5 v, or 2.7 v, whichever is higher. a minimum capacitor value of 1- f is required to be within 1 cm of the in pin. 10 layout 10.1 layout guidelines good pc layout practices must be used or instability can be induced because of ground loops and voltage drops. the input and output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have other currents flowing in them (kelvin connect). the best way to do this is to lay out c in and c out near the device with short traces to the in, out, and gnd pins. the regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground." it should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the device and the input and output capacitors. this was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. using a single point ground technique for the regulator and its capacitors fixed the problem. because high current flows through the traces going into v in and coming from v out , kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. 10.2 layout examples figure 31. sot-223 layout figure 32. wson lp38693 layout via connect to ground layer 1 en 2 adj 3 out c in c out 4 in r1 gnd r2 via connect to ground layer adj exposed pad on bottom (dap) 1 2 3 8 7 6 out en gnd in in r1 r2 c out c in
19 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 www.ti.com snvs324k ? january 2005 ? revised january 2016 product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 10.3 wson mounting the ngg0006a (no pullback) 6-lead wson package requires specific mounting techniques which are detailed in the ti application report leadless leadframe package (llp) snoa401 . referring to the section pcb design recommendations , it should be noted that the pad style which should be used with the wson package is the nsmd (non-solder mask defined) type. additionally, it is recommended the pcb terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection. the thermal dissipation of the wson package is directly related to the printed circuit board construction and the amount of additional copper area connected to the dap. the dap (exposed pad) on the bottom of the wson package is connected to the die substrate with a conductive die attach adhesive. the dap has no direct electrical (wire) connection to any of the pins. there is a parasitic pn junction between the die substrate and the device ground. as such, it is strongly recommend that the dap be connected directly to the ground at device pin 2 (gnd). alternatively, but not recommended, the dap may be left floating (no electrical connection). the dap must not be connected to any potential other than ground.
20 lp38691-adj , lp38693-adj , lp38691-adj-q1 , lp38693-adj-q1 snvs324k ? january 2005 ? revised january 2016 www.ti.com product folder links: lp38691-adj lp38693-adj lp38691-adj-q1 lp38693-adj-q1 submit documentation feedback copyright ? 2005 ? 2016, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? leadless leadframe package (llp) ( snoa401) ? semiconductor and ic package thermal metrics ( spra953 ) ? using new thermal metrics ( sbva025 ) ? thermal characteristics of linear and logic packages using jedec pcb designs ( szza017 ) 11.2 related links table 2 lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 2. related links parts product folder sample & buy technical documents tools & software support & community lp38691-adj click here click here click here click here click here lp38693-adj click here click here click here click here click here lp38691-adj-q1 click here click here click here click here click here lp38693-adj-q1 click here click here click here click here click here 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 20-jan-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lp38691qsd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l251b lp38691qsdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l251b lp38691sd-adj nrnd wson ngg 6 1000 tbd call ti call ti -40 to 125 l117b lp38691sd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l117b LP38691SDX-ADJ/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l117b lp38693mp-adj/nopb active sot-223 ndc 5 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 ljub lp38693mpx-adj/nopb active sot-223 ndc 5 2000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 ljub lp38693qsd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 llrb lp38693qsdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 llrb lp38693sd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l127b lp38693sdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l127b (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above.
package option addendum www.ti.com 20-jan-2016 addendum-page 2 green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lp38691-adj, lp38691-adj-q1, lp38693-adj, lp38693-adj-q1 : ? catalog: lp38691-adj , lp38693-adj ? automotive: lp38691-adj-q1 , lp38693-adj-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lp38691qsd-adj/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691qsdx-adj/nop b wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691sd-adj wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691sd-adj/nopb wson ngg 6 1000 180.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 LP38691SDX-ADJ/nopb wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693mp-adj/nopb sot-223 ndc 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 q3 lp38693mpx-adj/nopb sot-223 ndc 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 q3 lp38693qsd-adj/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693qsdx-adj/nop b wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693sd-adj/nopb wson ngg 6 1000 180.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693sdx-adj/nopb wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 package materials information www.ti.com 15-mar-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lp38691qsd-adj/nopb wson ngg 6 1000 210.0 185.0 35.0 lp38691qsdx-adj/nopb wson ngg 6 4500 367.0 367.0 35.0 lp38691sd-adj wson ngg 6 1000 210.0 185.0 35.0 lp38691sd-adj/nopb wson ngg 6 1000 203.0 203.0 35.0 LP38691SDX-ADJ/nopb wson ngg 6 4500 367.0 367.0 35.0 lp38693mp-adj/nopb sot-223 ndc 5 1000 367.0 367.0 35.0 lp38693mpx-adj/nopb sot-223 ndc 5 2000 367.0 367.0 35.0 lp38693qsd-adj/nopb wson ngg 6 1000 210.0 185.0 35.0 lp38693qsdx-adj/nopb wson ngg 6 4500 367.0 367.0 35.0 lp38693sd-adj/nopb wson ngg 6 1000 203.0 203.0 35.0 lp38693sdx-adj/nopb wson ngg 6 4500 346.0 346.0 35.0 package materials information www.ti.com 15-mar-2016 pack materials-page 2
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mechanical da t a ngg0006a www .ti.com s d e 0 6 a ( r e v a )
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